1. Field of the Invention
The present invention relates to an A/D converter (analog-to-digital converter), and more specifically, to a high speed A/D converter which can be formed in an integrated circuit of a small chip size.
2. Description of Related Art
Heretofore, various types of A/D converters have been proposed, and some of them are actually used in different fields. Among these A/D converters, a so-called "flash" A/D converter is known which includes comparators of the number corresponding to a required resolution of the A/D converter so that an input signal is simultaneously compared with different reference voltages by all the comparators and one digital signal is generated. One typical flash A/D converter is proposed by Andrew G. F. DINGWALL in IEEE J. Solid-State Circuits, vol. SC-14, pp 926-932, December 1979. The flash A/D converter requires a large number of elements, but can realize a conversion rate near to a response speed of the device. Therefore, the flash A/D converter can effectively be used in various fields requiring a high speed conversion.
Referring to FIG. 1, there is shown a typical conventional flash A/D converter, which is adapted to convert an input analog signal to a 6-bit digital signal. The shown A/D converter includes a resistor ladder 10 composed of a plurality of resistors R.sub.0 -R.sub.63 series-connected between a first reference potential +V.sub.ref and a second reference potential -V.sub.ref so that a connection tap T.sub.1 -T.sub.63 between each pair of adjacent resistors provides a different divided reference potential V.sub.1 -V.sub.63. The connection taps T.sub.1 -T.sub.63 are connected through a corresponding number of switches S.sub.11 -S.sub.631 to a corresponding number of connection nodes N.sub.11 -N.sub.631, respectively. On the other hand, an input 12 for an analog voltage signal V.sub.IN is connected to all the connection nodes N.sub.11 -N.sub.631 through switches S.sub.12 -S.sub.632 of the same number as that of the switches S.sub.11 -S.sub.631, respectively.
The connection nodes N.sub.11 -N.sub.631 are connected to one end of the same number of coupling capacitors CC.sub.1 -CC.sub.63, respectively. The other ends of these coupling capacitors CC.sub.1 -CC.sub.63 are connected to the same number of another connection nodes N.sub.12 -N.sub.632, respectively, which are in turn connected to inputs of inverting amplifiers A.sub.1 -A.sub.63. An output of each amplifier A.sub.1 -A.sub.63 are connected to the input of the amplifier per se through a short-circuiting switches S.sub.13 -S.sub.633, and further coupled to an encoder 14 having a 6-bit output 16.
The above switches S.sub.11 -S.sub.631, S.sub.12 -S.sub.632 and S.sub.13 -S.sub.633 are controlled by a switch controller 18.
An operation of the A/D converter is divided into a calibration period and a comparison period.
In the calibration period, the controller 18 causes to close the switches S.sub.11 -S.sub.631 and S.sub.13 -S.sub.633 and to maintain the switches S.sub.12 -S.sub.632 in an open condition. Therefore, the connection nodes N.sub.11 -N.sub.631 are applied with respective divided reference voltages V.sub.1 -V.sub.63 given by the respective taps T.sub.1 -T.sub.63 of the resistor ladder 10. Namely, the one electrode of the coupling capacitor CC.sub.1 -CC.sub.63 are brought to the divided reference voltages V.sub.1 -V.sub.63, respectively. On the other hand, since the input and output of each amplifier A.sub.1 -A.sub.63 are short-circuited by the closed associated switches S.sub.13 -S.sub.633, the nodes N.sub.12 -N.sub.632 and hence the other electrodes of the coupling capacitors CC.sub.1 -CC.sub.63 are brought to respective threshold voltages V.sub.TH1 -V.sub.TH63 of the amplifiers A.sub.1 -A.sub.63, respectively. Namely, each of the capacitors CC.sub.1 -CC.sub.63 stores an electric charge of the amount corresponding to the voltage difference (V.sub.1 -V.sub.TH1), . . . (V.sub.63 -V.sub.TH63).
In the comparison period succeeding to the calibration period, the controller 18 turns the switches S.sub.11 -S.sub.631 and S.sub.13 -S.sub.633 off and the switches S.sub.12 -S.sub.632 on. As a result, the nodes N.sub.11 -N.sub.631 are brought to the input voltage V.sub.IN. At this time, since the switches S.sub.13 -S.sub.633 are opened, the capacitors CC.sub.1 -CC.sub.63 maintain the electric charges corresponding to voltage differences (V.sub.1 -V.sub.TH1), . . . (V.sub.63 -V.sub.TH63).
In general, an inverting amplifier is set to have a threshold voltage V.sub.TH at a high point in the gain range of the inverting amplifier. Therefore, if the input voltage of each inverting amplifier A.sub.1 -A.sub.63 is shifted slightly from the threshold voltage V.sub.TH -V.sub.TH63 of the inverting amplifier per se, the amount of the shift is amplified so that the inverting amplifier outputs either a high voltage H or a low voltage L, which can in turn correspond to "1" and "0" of a binary number. If the input voltage V.sub.IN is smaller than one divided reference voltage V.sub.i, an input voltage of an inverting amplifier A.sub.i (i=1-63) becomes lower than a threshold voltage V.sub.THi of the amplifier A.sub.i, so that the amplifier A.sub.i generates a high voltage output H corresponding to a logic level "1". But, if the input voltage V.sub.IN is larger than one divided reference voltage V.sub.i (i=1-63), an input voltage of an inverting amplifier A.sub.i becomes higher than a threshold voltage V.sub.THi (i=1-63) of the amplifier A.sub.i, so that the amplifier A.sub.i generates a low voltage output L corresponding to a logic level "0".
As seen from FIG. 1, the divided reference voltages V.sub.1 . . . V.sub.63 come under the relation V.sub.1 &lt;V.sub.2 &lt; . . . &lt;V.sub.63. Therefore, if the input voltage V.sub.IN is between the first reference voltage +V.sub.ref and the second reference voltage -V.sub.ref, an inverting amplifier A.sub.i which has been applied with a divided reference voltage V.sub.i fulfiling the relation V.sub.IN &gt;V.sub.i, the inverting amplifier A.sub.i will generate a low logic voltage output L. On the other hand, an inverting amplifier A.sub.i which has received an divided reference voltage V.sub.i fulfiling the relation V.sub.IN &lt;V.sub.i will generate a high logic voltage output H.
The outputs of all the amplifiers A.sub.1 -A.sub.63 are supplied to the encoder 16, where the pattern of the amplifier outputs is detected and converted to a 6-bit digital signal.
In the A/D converter as mentioned above, when either the switches S.sub.11 -S.sub.631 or the switches S.sub.12 -S.sub.632 are closed to form wiring circuits to the associated coupling capacitors CC.sub.1 -CC.sub.63, respectively, the nodes N.sub.11 -N.sub.631 will have parasitic capacitances CS.sub.1 -CS.sub.63, respectively. These parasitic capacitances CS.sub.1 -CS.sub.63 are charged or discharged every time the voltages of the respective nodes N.sub.11 -N.sub.63 are changed between the respective divided reference voltages V.sub.1 -V.sub.63 and the analog input voltage V.sub.IN. But, in order to ensure precise A/D conversion of the input analog voltage V.sub.IN, the charge/discharge time is required to be sufficiently smaller than the calibration period and the comparison period.
Specifically, in the comparison period, the charge/discharge time is determined by an impedance of a source supplying the analog voltage V.sub.IN, a resistance of each switch S.sub.12 -S.sub.632 and each parasitic capacitance CS.sub.1 -CS.sub.63. On the other hand, in the calibration period, the charge/discharge time is determined by an impedance of the resistor ladder 10 generating the respective divided reference voltages, a resistance of each switch S.sub.11 -S.sub.631 and each parasitic capacitance CS.sub.1 -CS.sub.63. Therefore, in order to shorten the charge/discharge time, it is preferable to decrease the resistance of each resistor R.sub.0 -R.sub.63 in the resistor ladder 10.
Furthermore, in the case that the input voltage V.sub.IN will gradually change in comparison with the A/D conversion rate, electric charges stored in the parasitic capacitances CS.sub.1 -CS.sub.63 will fluctuate the respective divided reference voltages V.sub.1 -V.sub.63. For example, before the comparison period is shifted to the calibration period, the analog input voltage V.sub.IN is applied through the switch S.sub.12 to the node N.sub.11 so that the parasitic capacitance CS.sub.1 stores an electric charge, and thereafter, when it is shifted to the calibration period, the electric charge of the parasitic capacitance CS.sub.1 influence the divided reference voltage V.sub.1 through the closed switch S.sub.11. This fluctuation caused by the parasitic capacitance is difficult to correct, since the amount of electric charge stored in the parasitic capacitance will be varied in dependence of the analog input voltage V.sub.IN. In the conventional A/D converter, accordingly, the resistors R.sub.0 -R.sub.63 have to have a low resistance to the extent that the divided reference voltages V.sub.1 -V.sub.63 are not influenced.
However, the decrease in the resistance of the resistors R.sub.0 -R.sub.63 will result in increased dissipation current. This will require an A/D converter device to have not only a large current density but also a large chip size. The former is not preferable in the view point of reliability, and the latter is not convenient in cost performance.